In this paper, a design method is described for very low sensitivity fully-balanced narrow-band band-pass switched-capacitor filters (SCF's) whose worst-case sensitivities of the amplitude responses become zero at every reflection zero. The proposed method is based on applying the low-pass to high-pass transformation, the pseudo two-path technique and the capacitance-ratio reduction technique to very low sensitivity low-pass SC ladder filters. A design example of the band-pass SCF with a quality factor Q250 is given to verify the proposed method. The remarkable advantages of this approach are very low sensitivity to element-value variations, a small capacitance spread, a small total capacitance, and clock-feedthrough noise immunity inside the passband.

New AC-DC converters using switched-capacitor (SC) transformers are presented. The features of these circuits are as follows. (1) It does not contain any magnetic material. (2) The inrush current of the proposed converter is very small as compared with that of a condenser-input-type rectifier circuit. (3) It is realizable in a hybrid IC form. (4) It excels in size and weight when compared with reactor-type switching regulators of the same output power. As an example, an AC-DC converter using step-up SC transformers was built and tested to confirm the characteristics. The measured characteristics showed good agreement with the calculated ones.

This paper deals with the method for generation of maximal-period sequences which are designed by properly quantizing the variable state of a class of one-dimensional piecewise-linear onto maps. We confirmed that the proposed method enables us to generate many maximal-period sequences from such maps including De-Bruijn cases.

This paper describes a single-bit parallel processor specified to Boltzmann Machine. The processor has SIMD (Shingle Instruction Multiple Data stream) type parallel architecture and every processing element (PE) has a single-bit ALU and a local memory storing connected weights between neurons. Features of the processor are large scale parallel processing a number of the simple single-bit PEs and effective expansion realized by multiple chips connected simple bus lines. Moreover, it is enhanced that the processing speed can be independent of the number of the neurons. We designed the PE using 1.2 µm CMOS process standard cells and confirmed the high performance using CAD simulations.

A method for circular pattern recognition in a binary image and its implementation onto an FPGA are described. The proposed method is based on the template matching method using a modified matching degree. This method is implementable onto an FPGA and can realize a real-time system. The usefulness of the proposed method was confirmed by numerical simulations. The real-time performance was confirmed by experiments on the FPGA designed by using Verilog-HDL CAD tool.

A maximum and a minimum circuits with multiple inputs are proposed. The operating speeds of these circuits are independent of the number of the inputs. Since the proposed circuits consist of only NMOS transistors, they can be implemented in semi-custom IC forms. A potential application of these circuits is a real-time fuzzy controller.

New OTA-based analog circuits for realizing fuzzy membership functions and maximum (MAX) and minimum (MIN) operations are proposed. The synthesis of these circuits based on a bounded-difference operation and their SPICE simulations are described.

This paper presents design of spreading codes for asynchronous DS-CDMA systems. We generate maximal-period sequences with negative auto-correlations based on one-dimensional maps with finite bits whose shapes are similar to piecewise linear chaotic maps. We propose an efficient search algorithm to find such maximal-period sequences. This algorithm makes it possible to find many kinds of maximal-period sequences with sufficiently long period for practical CDMA applications. We also report that maximal-period sequences can outperform conventional Gold sequences in terms of bit error rate (BER) in asynchronous DS-CDMA systems.

A circuit design of a CMOS integrable heartbeat spike-pulse detection circuit is proposed in this paper. This circuit is developed to be implemented on a small-sized RFID sensor tag (which we call a smart RFID tag throughout this paper) implanted in a transgenic mouse. This circuit can detect only spike pulses with magnitude higher than the prescribed level from a mouse's heartbeat signal, which is sensed by a small microphone sensor and/or an electrocardiogram (ECG) microsensor attached to the RFID tag. The proposed circuit features robustness to the device tolerances and temperature variations thanks to its auto-bias technique based on good device matching and its switched-capacitor auto offset-canceling technique. The circuit was fabricated by a standard 0.35 µm CMOS process and works at a supply voltage of 3 V and dissipates less than 800 µW.

A low-sensitivity lowpass switched-capacitor filter (SCF) whose worstcase sensitivity becomes zero at zero frequency is presented. The proposed SCF is realized with the fully balanced SC circuits using the op-amps which can provide the outputs of both signs.

The realization and the design of three types of low-sensitivity leapfrog switched-capacitor filters (SCF's) are proposed. These SCF's realized with new differential-mode building blocks exhibit an excellent reduction in worstcase sensitivity to component variations. The design for each proposed SCF was confirmed by the experiment. Since the proposed SCF's are all parasitics-compensated, they are realizable in MOS IC forms.

Switched capacitor (SC) circuits for realizing piecewise-linear S- and Z-shaped variable threshold functions are proposed. With these circuits, basic nonlinear functions in fuzzy logic and neural networks can be synthesized in the form suitable for MOS VLSIs.

A simple CMOS Vth-adjustment method for a common-source floating-gate MOSFET(FG-MOSFET) is proposed. The apparent threshold voltage Vtha of an FG-MOSFET can be defined by a reference voltage Vref and/or a reference current Iref being almost irrelevant to the pre-stored charge on the floating gate.

A new theorem is proposed on BIBO (Bounded Input Bounded Output) stability of a general feedback amplifier circuit formulated by BIBO operators. The proposed theorem holds for both linear and nonlinear BIBO operators. The meaning of this theorem is clarified by applying it to continuous-time linear cases.

Reducing the power consumption of capsule endoscopy is essential for its further development. We introduce K-SVD dictionary learning to design a dictionary for sparse coding, and improve reconstruction accuracy of capsule endoscopic images captured using compressed sensing. At a compression ratio of 20%, the proposed method improves image quality by approximately 4.4 dB for the peak signal-to-noise ratio.

This paper presents four-valued dynamic encoder and decoder circuits for CMOS multivalued logic systems. The circuits presented here are implemented using a new logical voltage generator and a simplified pass transistor circuit. The logical voltage generator operates with higher speed than the conventional circuit. And the simplified pass transistor circuit contributes to reducing the number of transistors. these circuits have several advantages such as a simple configuration, high speed and low power dissipation. The circuit simulation for the proposed circuits has been performed using SPICE2 program.

A parasitic compensated switched-capacitor (SC) integrator using a fully differential structure is presented. The effect of the imperfect matching of the capacitors or of the parasitic capacitances appears only in the form of the variation in the integrator gain.

In this paper, a novel chaos circuit with long working-life is proposed. The proposed circuit consists of NMOS-coupled discrete-time chaotic cell circuits. By employing chaos synchronization phenomenon, the proposed circuit can achieve long working-life. Since the proposed circuit is less susceptible to breakdown, the rate of the acceptable product for chaos IC can be improved. Furthermore, thanks to the coupling by using NMOSFET's, the loss of the connection line between chaotic cell circuits can be controlled electronically. Therefore, the proposed system designed by using switched-current (SI) techniques is useful as an experimental tool to analyze chaos synchronization phenomena. The validity of the proposed circuits is confirmed by computer simulations and experiments.

A multiple-input switched-capacitor DC-DC converter which can realize long battery runtime is proposed in this letter. Unlike conventional converters for a back-lighting application, the proposed converter drives some LEDs by converting energy from solar cells. Furthermore, the proposed converter can charge a lithium battery when an output load is light. The validity of circuit design is confirmed by theoretical analyses, simulations, and experiments.